1. Field of the Invention
The present invention is directed in general to the field of semiconductor devices. In one aspect, the present invention relates to the fabrication of metal gate electrodes used in semiconductor devices.
2. Description of the Related Art
As the size and scaling of semiconductor device technology is reduced, the requirements for device design and fabrication—such as reducing the length of gate electrodes—continue to tighten. There are also increased requirements for transistor performance (e.g., increased speed, lower power dissipation) with newer technologies. An additional challenge posed by decreasing feature sizes is that aspects of device design and fabrication that previously gave rise to only second-order effects in long-channel devices can no longer be ignored. For example, the reduced scaling of channel length and gate oxide thickness in a conventional MOS transistor exacerbates problems of polysilicon gate depletion, high gate resistance, high gate tunneling leakage current and dopant (i.e., boron) penetration into the channel region of the device. As a result, CMOS technology is increasingly replacing silicon dioxide gate dielectrics and polysilicon gate conductors with high dielectric constant (high-k) dielectrics in combination with gate electrodes formed from one or more metal layers. With such technologies, metal gates not only obviate gate-depletion and boron-penetration effects, but also provide a significantly lower resistance.
While high-k dielectrics in conjunction with metal gate electrodes advantageously exhibit improved transistor performance, the metal layer portion of the gate electrodes can be difficult to etch with conventional gate etch techniques, making it difficult to control the gate length of such electrodes. But when transistors gates formed from polysilicon and metal layer are etched in a conventional manner, wide metal gate foot or ledge features are observed that extend far beyond the polysilicon gate. An example of such a foot/ledge feature is shown in FIG. 1, which depicts a partial cross-sectional view of a semiconductor structure 1 including a substrate 2, a dielectric layer 6 and a conventionally etched gate electrode 3 formed from a metal layer 4 and a polysilicon layer 8. With existing gate etch processes, the gate electrode 3 includes wide metal gate feet or ledges 5 formed from the metal layer 4 and extending beyond the polysilicon gate 8, both horizontally along a shelf region 7 and then down a tapered region 9 to the dielectric layer 6. These feet 5 can significantly increase the transistor length and degrade transistor electrical performance. The feet also would have pitch (line to line) spacing dependencies due to polymerization which is impacted by shadowing. These feet therefore will vary in dimension, resulting in not only degraded performance, but variable performance. Prior attempts to control the fabrication of metal gates have relied on overly complex processes that sidestep or ignore the sidewall profile issues created by metal etch processes.
Accordingly, a need exists for an improved metal gate electrode and manufacture method for reducing or eliminating the metal feet or ledges or extrusion. There is also a need for a controlled fabrication process that reliably produces metal gate electrodes with improved sidewall profiles. In addition, there is a need for improved semiconductor device structure and manufacturing process to overcome the problems in the art, such as outlined above. Further limitations and disadvantages of conventional processes and technologies will become apparent to one of skill in the art after reviewing the remainder of the present application with reference to the drawings and detailed description which follow.
It will be appreciated that for simplicity and clarity of illustration, elements illustrated in the drawings have not necessarily been drawn to scale. For example, the dimensions of some of the elements are exaggerated relative to other elements for purposes of promoting and improving clarity and understanding. Further, where considered appropriate, reference numerals have been repeated among the drawings to represent corresponding or analogous elements.